Find a component and its ports

diode keeps the anode on the left and cathode on the right. Use type=standard|schottky|zener|led.

transistor accepts type=npn|pnp|nmos|pmos. BJT and FET names point to the same physical terminals.

port marks the edge of a system and exposes in and out.

ground has one in port above the symbol. Choose style=signal, earth, or chassis; the default is signal.

The built-in gates are and, nand, or, nor, xor, and not.

Use inputs=1..32, outputs=1..32, and standard=ieee|iec. not always has one input. Ports are in1..inN and out1..outN; in and out alias the first pins.

hadamard exposes in and out. cnot adds control and target. qgate is the custom operator block and accepts quoted parameter, matrix, and phase rows.

All visible text supports micro-math.

ic accepts quoted, comma-separated left, right, top, and bottom pin lists. Each name becomes a case-sensitive port, and the body grows to fit the longest side.

Use the real pin name in a connection, for example U1.DATA. in and out fall back to the first suitable input and output sides.

class accepts semicolon-separated attributes and operations, plus an optional stereotype and width. Its height grows with the rows, and its width grows to fit the widest visible string.

package and note accept width and height. They are normal nodes, not automatic layout containers.

Every UML node exposes left, right, top, bottom, in, and out.

actor, initial, and final need no options. usecase accepts width and height. state accepts semicolon-separated details and an optional width.

Use association for participation, include and extend between use cases, and transition for state flow.

lifeline accepts width and height. Alongside the normal side ports, leftNN and rightNN place a port NN units from the top of the lifeline.

Use message for an open arrow. Add dashed for a reply and label="..." for message text.